AEC G4 - 4th GENERATION ACOUSTIC ECHO CANCELLER

Generation 4 Acoustic Echo Canceller C55x, TMS320C6000x, ARM® Cortex-A8

Acoustic Echo is caused by direct and indirect feedback from speaker to microphone. In order to combat the echo phenomenon, an echo canceller is employed. Today’s echo cancellers use sophisticated algorithms running on high speed Digital Signal Processors (DSPs)

The Adaptive Digital Technologies acoustic echo canceller electronically removes both direct coupling and reflected echo, enabling true full-duplex hands-free telephony both mobile phones, desktop speakerphones, and hands-free intercoms. Adaptive Digital has been developing echo canceller technology for over ten years. This acoustic echo canceller (AECG4) is the fourth generation (G4) acoustic echo canceller offered by Adaptive Digital.

The fourth-generation canceller includes a noise reduction feature, as well as the typical anti-howling, nonlinear processing, and double-talk detection found in the first generation AEC. The acoustic noise reduction feature is particularly useful during speakerphone calls where there is background noise present such as an exhaust fan, and in noisy outdoor environments.

By using Adaptive Digital’s acoustic echo canceller to eliminate this unwanted echo and reverberating interference, echo-free conversation can be achieved.

Data Sheet - .pdf

AVAILABILITY

ADT AEC G4 is available on the TMS320™ DSP Family
The AEC supports the TI xDAIS interface.
Target Processors:
C55x™DSP, C64x™DSP, C64x+™DSP, C67x+™DSP, and C674x™DSP Generations

ARM® CORTEX-A8

FEATURES

Gen 4

  1. Functions are C-callable
  2. Multiple channel operation
  3. Parameters are user configurable
  4. Non-linear processor
  5. Excellent voice quality
  6. Fast Convergence
  7. No divergence due to doubletalk
  8. Automatic Gain Control
  9. Noise reduction
  10. Equalization
  11. xDAIS compliant


SPECIFICATION

C55x - CPU and Memory Utilization

All Memory usage is given in units of byte.

Processor MIPS Program Data Channel Scratch Constants
C55x 50* 40K 42K 35K 4K 3.6K

* The MIPS and memory based on the 64ms tail length setting.

Last update: 02/15/2010

C6000+ CPU Utilization and Memory Requirements

MEMORY REQUIREMENTS

All Memory usage is given in units of byte.

Processor Program Data Constants
C64 49420 104 1684
C64x+ 73216 481 1671
C674x 62592 521 1695

Notes:
All memory specifications including alignment requirements are given in units of 8 bit bytes.
Memory specified for builds that include both AGC and Noise Reduction

The variable length memory sections are further sub-divided into three categories:
Common: initialized data (tables) that are common to all channels/instances

Scratch: data that is used during a frame of AEC execution, but do not need to be preserved from one frame to the next. Scratch memory may be shared between channels that do not preempt each other.

Per Channel: data that is used by a particular channel that must persist from the execution of one frame to the next.

The length of each variable length memory section is a function of some echo canceller setup parameters, as shown in the following table Memory Usage Affecting Parameters:

Sample configurations

  1. SamplingRate
  2. ActiveTailLength
  3. TotalTailLength
  4. Build Variant
C64x
Parameters Section
Sampling Rate (Hz) Active Tail Length (msec) Total Tail Length (msec) Channel Scratch Common
8000 32 64 20224 3376 4032
8000 64 128 34944 3756 816
8000 128 256 53816 8128 1024
16000 32 64 38048 3756 816
16000 64 128 73632 4524 816
16000 128 256 59744 14720 2048

Notes:
Memory specified for builds that include both AGC and Noise Reduction

C64x+/ C674x
Parameters Section
Sampling Rate (Hz) Active Tail Length (msec) Total Tail Length (msec) Channel Scratch Common
8000 32 64 20224 3376 4032
8000 64 128 34944 3756 816
16000 32 64 38048 3756 816
16000 64 128 73632 4524 816

Notes:
Memory specified for builds that include both AGC and Noise Reduction

 

C6000x CPU UTILIZATION

The following table contains CPU utilization of the AEC as a function of sampling rate, tail length, and processor. The CPU utilization is given in Millions of Instruction Cycles Per Second per channel. This is also referred to as MIPS, which we also equate to processor clock speed specified in MHz.


Parameters
Sampling Rate (Hz) Active Tail Length (msec) Total Tail Length (msec) C64X+ C674X
8000 32 64 26 25
8000 64 128 32 31
16000 32 64 68 57
16000 64 128 85 83

 

ARM CORTEX-A8
CPU UTILIZATION & MEMORY REQUIREMENTS


All Memory usage is given in units of byte. 

AEC-G4 * MIPS
Cortex-A8
Program Memory Data Memory Scratch Memory Per-Channel Data Memory
8000/ 32/ 64 52 96020 1104 3376 (8000kHz) 20224 (8000kHz)

*Sampling Rate (Hz)/ Active Tail Length(msec))/ Total Tail Length (msec)

FUNCTION

AECG4_ADT_create(…)                     Create and initializes an echo canceller channel
AECG4_ADT_applyl(…)                      Executes cancellation function
AECG4_ADT_backgroundHandler(…)   Handles background calculations
AECG4_ADT_delete(…)                      Deletes an echo canceller channel

 

 

 

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