ECHO CANCELLATION CHIP SOLUTION - LINE & NETWORK

HDEC CHIP - C6424- High Density, Low-cost Echo Cancellation Chip
 VOICEXCELLENCE™

PRODUCT DESCRIPTION

The Adaptive Digital Technologies high-density echo canceller chip (ADT HDEC-168 C6424)is a patented carrier-class ITU G.168 compliant PCM network echo canceller chip. This chip is based upon Adaptive Digital’s AT&T certified soft echo canceller running on the Texas Instruments high performance low-cost TMS320C6424 Digital Signal Processor (DSP). The chip supports both T-1 (mu-law) and E-1 (a-law) configurations.

The ADT EC-168 C6424 features Adaptive Digital’s proprietary Bellcore/Telcordia and ITU compliant DTMF detector.

The HDEC-168 C6424 uses two TDM serial ports, one for the receive side of the canceller and the other for the send side of the canceller. The TDM serial ports are fully programmable to allow connection to nearly any type of serial bus.

Control of the HDEC-168 C6424 is facilitated by using an ANSI “C” set of API functions that are provided to run on a host processor. These functions configure and control the EC-168 as well as return status information to the host application.

FEATURES

Echo Canceller

  1. Certified by AT&T Voice Quality Lab

  2. ITU G.168-2002 Compliant

  3. Compliant using all ITU hybrid models

  4. Supports up to 120 channels
    [THIS FEATURE APPLIES TO EC+DTMF, NOT JUST EC]

  5. Adaptive Non-linear processor

  6. No divergence due to double-talk

  7. G.164/G.165 Tone Disabler

DTMF Detector

  1. ITU Q.24 compliant

  2. Meets Bellcore GR506, ITU Q455 specifications

  3. Robust detection

  4. Low false alarm rate

SERIAL PORT CONFIGURATION

The EC-168 C6424 can operate using either one or two TDM serial ports. Although time slot mapping can be done, there are default time slot mappings for both the single port and the two port configurations. If two serial ports are used (ports 0 and 1), a single echo canceller channel operates on a given time slot on both serial ports. For example, echo canceller channel 0 is connected to serial port 0, time slot 0 for its receive side and it is connected to serial port 1, time slot 0 for its send side.

If a single serial port is used, the receive and send sides use even and odd time slots. In this case, the receive side would be connected to serial port 0, time slot 0 and the send side would be connected to serial port 0, time slot 1.


In the block diagram of the EC-168 C6424 chip. The echo canceller is inserted into a bi-directional multi-channel PCM stream. The DSP’s McBSP (Multi-Channel Buffered Serial Ports) handle the PCM interface. We refer to the two bi-directional PCM interfaces as the “A” interface and the “B” interface. Traditionally, a network echo canceller is designed to cancel echo that occurs only at one end of the link. This end of the link is referred sometimes as the “near end” or “send side”. The other end of the link is referred to as the “far end” or “receive side”. Each side of the echo canceller has an input and an output. The receive and send inputs and outputs are often labeled Rin, Rout, Sin, and Sout respectively.

The EC-168 C6424 can be configured in the traditional way, but it can also be configured to cancel echo from both ends. In the later case, two channels of resources will be required for each full-duplex TDM channel.

The EC-168 C6424 is controlled via the DSP’s Host Port Interface (HPI). In order to simplify the use of the EC-168, the EC-168 ANSI “C” API software resides on a host processor. This API provides an abstraction layer that hides the details of the control mechanisms from the host application.

The API functions are listed below. For more detailed information, please refer to the ADT EC-168 ‘C6424 Chip users guide.

ADT_EC168Configure( .. )

ADT_EC168SetupChannel( … )

ADT_EC168TeardownChannel( … )

ADT_EC168ControlChannel( … )

ADT_EC168GetChannelStatus( … )


 

 

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