G.722 | G.722 PLC HD Codec

G.722 PLC - ITU Audio Codec with Packet Loss Concealment

G.722 includes a proprietary VAD/CNG/DTX – (Voice Activity Detection, Comfort Noise Generation / Discontinuous Transmission) features.

Coding Rate: 48, 56, or 64 kbps, and 23.85 kbps
Sampling Rate: 16 kHz
Delay: 125 microseconds

Platforms

Availability

Platforms	G.722	G.722 with PLC	G.722 AnnexIV
Arm ® Devices – Armv7-A / Armv8-A \|\| Armv7-M / Armv8-M \|\| Legacy M3, ARM9E	Armv7-A / Armv8-A \|\| Armv7-M / Armv8-M \|\| Legacy M3, ARM9E /11	Armv7-A / Armv8-A \|\| Armv7-M / Armv8-M \|\| Legacy M3, ARM9E /11	Armv7-A / Armv8-A \|\| Armv7-M / Armv8-M \|\| Legacy M3/ARM9E /11
Texas Instruments – TI TMS320C6000 C64x/C64x+/C66x, C674x, TMS320C5000 C55x / C54x	C674x / C64x / C55x / C54x	—	—
Windows x86 (32-bit) / x64 (64-bit)	—	Win 32-bit LIB / DLL	Win 32-bit LIB / DLL
Linux 32-bit / 64-bit	—	Linux 32-bit	Linux 32-bit

ADT G.722 is available on the above Platforms: Other configurations are available upon request.

Features

Functions are C-callable.
Multi-channel capable
Can be integrated with echo cancellers, VOX and tone detection/regeneration.
Can be integrated with G.711/G.728 to provide the audio portion of the H.320 video standard.
The encoder and decoder meet all ITU G.722 compliance data files.
C55x and ARM – Optional Packet Loss Concealment (PLC): Proprietary technique developed by Adaptive Digital.
ARM, Win32, and i686 – Optional PLC compliant to G.722 Appendix IV Standard

Description

The Adaptive Digital Technologies G.722 Audio Coder is a real-time implementation of the ITU G.722 audio coder. It is used with many applications that require audio frequency bandwidth coding such as video conferencing, multimedia, and speaker/microphone digital telephony. The G.722 audio coder encodes 16 kHz sampled audio signals for transmission over 48, 56, and 64 kbps channels, and provides 7 k Hz of audio bandwidth.

Adaptive Digital’s G.722PLC is a high quality low-complexity proprietary algorithm for packet loss concealment with G.722. G.722 on TI’s C55x™DSP, and ARM devices support an optional Packet Loss Concealment (PLC) features on the decoder side. We also offer a PLC algorithm compliant to the G.722 Appendix IV Standard.

Adaptive Digital’s implementation of G.722 includes a proprietary VAD/CNG/DTX (Voice Activity Detection, Comfort Noise Generation / Discontinuous Transmission) feature. While many VoIP and wireless codecs include this type of functionality as part of the standard, G.722 does not. Adaptive Digital therefore implemented a proprietary implementation that is voice-quality-optimized for the G.722 codec. Adaptive Digital plans to make this available on other platforms in the near future.

In Appendix IV, the decoder comprises three stages: lower sub-band decoding, higher sub-band decoding and quadrature mirror filter (QMF) synthesis. In the absence of frame erasures, the decoder structure is identical to ITU-T G.722, except for the storage of the two decoded signals, of the higher and lower sub-bands. In case of frame erasures, the decoder is informed by the bad frame indication (BFI) signalling. It then performs an analysis of the past lower-band reconstructed signal and extrapolates the missing signal using linear predictive coding (LPC), pitch-synchronous period repetition and adaptive muting. Once a good frame is received, the decoded signal is cross-faded with the extrapolated signal. In the higher sub-band, the decoder repeats the previous frame pitch synchronously, with adaptive muting and high pass post-processing. The adaptive differential pulse code modulation (ADPCM) states are updated after each frame erasure.

Specification Tables

NOTE: We specify MIPS (Millions of Instructions Per Second) as MCPS (Millions of Instruction Cycles Per Second). Unless otherwise specified, peak MIPS are indicated.

ARM Devices

G.722 Armv9-A Neoverse N2

CPU Utilization
The ARM Neoverse is a group of 64-bit ARM processor cores.

Function	MIPS
G.722 Encode/Decode	2.6

G.722 Armv8-A Cortex-A53 / A72

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS Cortex- A53	MIPS Cortex-A72	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode/Decode	5.7	3.8	7k	2k	150

G.722 Armv7A Cortex-A8 / A9 / A15 / A17

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS Cortex- A8 / A9 / A15	Program Memory	Data Memory	Per Channel Data Memory	Scratch Memory
G.722 Encode	6.1	6996	1284	146	624
G.722 Decode	5.4	6996	1284	146	624

G.722 with PLC Armv7A Cortex-A8 / A9 / A15 / A17

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	13.5	42 K	7.6 K	288
G.722 Decode	7.4			288
G.722 Decode w/ PLC Enable	11.1			4248

G.722 Annex IV Cortex-A8 / A9 / A15 / A17

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	13.5	43 K	7.7 K	288
G.722 Decode	7.4			288
G.722 Decode w/ PLC Enable	11.1			2020

G.722 Cortex-M4

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS Cortex-M4	Program Memory	Data Memory	Per Channel Data Memory	Scratch Memory
G.722 Encode	13.4	6996	1284	146	624
G.722 Decode	13.0	6996	1284	146	624

G.722 with PLC Cortex-M4

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	16.1	30 K	1.5 K	288
G.722 Decode	15.2			288
G.722 Decode w/ PLC Enable	22.3			4248

G.722 with PLC Cortex-M33/M35 – estimate

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	12.9	30 K	1.5 K	288
G.722 Decode	12.2			288
G.722 Decode w/ PLC Enable	17.8			4248

* Adaptive Digital’s G.722 ARM-Cortex-A device family version also has optional packet loss concealment (PLC) plus a proprietary VAD/CNG/DTX feature.

G.722 Annex IV Cortex-M4

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	16.1	30 K	1.7 K	288
G.722 Decode	15.2			288
G.722 Decode w/ PLC Enable	21.3			2020

G.722 Annex IV Cortex-M33/M35 – estimate

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	12.9	30 K	1.7 K	288
G.722 Decode	12.2			288
G.722 Decode w/ PLC Enable	17			2020

G.722 ARM9e / ARM11 Legacy

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Device	MIPS	Program Memory	Data Memory	Per Channel Data Memory
ARM9e	25.5	5.3 K	1.3 K	292
ARM11	41.4	5.3 K	1.3 K	292

G.722 with PLC ARM9e / ARM11

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	11.3	34 K	7.6 K	288
G.722 Decode	11			288
G.722 Decode w/ PLC Enable	16.9			4248

*PLC Decode MIPS measurement taken with simulated 2% packet loss.

G.722 Annex IV ARM9e / ARM11

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	11.3	58 K	7.7 K	288
G.722 Decode	11			288
G.722 Decode w/ PLC Enable	16.9			2020

TI Processors

G.722 C64x / C64x+ / C66x / C674x

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	5.3	4768	1426	192
G.722 Decode	4.8	4768	1426	192

G.722 C64x / C64x+ Variant

PROCESSES 2 CHANNELS SIMULTANEOUSLY THEREBY BY REDUCING THE PER CHANNEL MIPS BY A FACTOR OF 2
CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Device	MIPS	Program Memory	Data Memory	Per Channel Data Memory
Encode Variant	2.84	8000	1664	364
Decode Variant	2.36	8000	1664	364

Variant *Note: Above numbers for non-cached. After caching, cycle count will improve.

G.722 C55x

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Device	MIPS	Program Memory	Data Memory	Per Channel Data Memory
Encode	6.0	2717	1212	164
Decode	4.8	2717	1212	164
Decode with PLC* enable	5.5	3811	609	3528

*Note: Proprietary technique developed by Adaptive Digital.

G.722 C54x

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
Encode	7.5	1438	654	80
Decode	6.4	1438	654	80

Linux

G.722 Annex IV i686

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	10.8	51 K	7.7 K	288
G.722 Decode	10.5			288
G.722 Decode w/ PLC Enable	10.8			2020

G.722 with PLC i686

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	11.2	27 K	7.6 K	288
G.722 Decode	11.2			288
G.722 Decode w/ PLC* Enable	13.9			4248

Windows

G.722 with PLC Win DLL

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	14.5	12 K	9.3 K	288
G.722 Decode	12.9			288
G.722 Decode w/ PLC Enable	14.9			4248

G.722 with PLC WIN Static Lib

CPU Utilization & Memory Requirements
All Memory usage is given in units of byte.

Function	MIPS	Program Memory	Data Memory	Per Channel Data Memory
G.722 Encode	13.9	12 K	9.3 K	288
G.722 Decode	12.9			288
G.722 Decode w/ PLC Enable	14.9			4248

API Functions

API function call summary

ResetG722 ()Initializes the G.722 audio coder Channel structures

EncodeG722 () Executes the G.722 encoder

DecodeG722 () Executes the G.722 decoder